Design of a new BPSK modulator

Abstract

In recentlj the design of modulator algorithms for wireless communication,systems by using cdgital circuits is widely read' ed. Moreover, it is crucial that resource utilization of the selected algorithm is reduced. In this paper, u modulator architecture which has lower RAM bit that of conventional BPSK is proposed for BPSK (Binary Phase Shift Keying) modulation technique that is used widely wireless communication systems. The architecture can achieve to save RAM bit utilization by up to 87,5% with respect to conventional BPSK, In addition, a real-time message signal is applied on ADC, (Analog to DIgitul Converter) which is integrated on Altera DE -0 Nano FPGA (Field Programmable Gate Array) in the paper. It is shown that proposed strmagre is practically realizable by achieving of message sIgnai in output of DAC (Digital to Analog Converter-) after modulation and demodulation processes,