FPGA based programmable embedded Intrusion Detection System

Abstract

In this article, the design of a Field Programmable Gate Array (FPGA) based real time Intrusion Detection System (IDS) is presented. The embedded system first summarizes and normalizes the packets and then determines whether there is an attack or not using this summary according to the naive bayesian algorithm. The packet summaries which play an important role in the accurate classification of the packets include data such as the IP numbers of the packets, port numbers, protocol types and packet length. Real time Intrusion Detection System (IDS) was designed in the Altera Cyclone III based FPGA development environment and tested. As a result of the tests performed, appropriate results were obtained. Copyright 2010 ACM.