Simultaneously Realization of Image Enhancement Techniques On Real-Time Fpga
| dc.contributor.author | Yildirim, Muhammed | |
| dc.contributor.author | Cinar, Ahmet | |
| dc.date.accessioned | 2026-08-12T16:42:02Z | |
| dc.date.issued | 2019 | |
| dc.department | Fırat Üniversitesi | |
| dc.description | International Conference on Artificial Intelligence and Data Processing (IDAP) -- SEP 21-22, 2019 -- Inonu Univ, Malatya, TURKEY | |
| dc.description.abstract | Image Processing Techniques have recently become one of the most popular and widely used technologies. Image processing techniques are widely used in many areas [1]. Particularly in real-time applications, imaging and processing in a very short time is of great importance. In this paper, Spatial Domain Techniques which are commonly used in almost all Image Processing Techniques are discussed. Field Programmable Gate Array (FPGA) architecture is used in order to perform the operations as soon as possible while applying image processing techniques.Since the FPGA architecture has the ability to perform parallel processing, it will shorten the processing time and the efficiency will increase [2]. Also, the ability to use FPGA over and over again provides an extra advantage.In this paper, applications are performed using the Vivado program using the verilog hardware identification language. In addition to the simultaneous acquisition of numerical data, corresponding visual figures have been developed in the MATLAB program so that the subject can be better understood. | |
| dc.description.sponsorship | IEEE Turkey Sect,Anatolian Sci,Inonu Univ, Comp Sci Dept,Inonu Univ, Muhendisli Fakultesi | |
| dc.identifier.doi | 10.1109/idap.2019.8875959 | |
| dc.identifier.orcid | 0000-0003-1866-4721 | |
| dc.identifier.scopus | 2-s2.0-85074883276 | |
| dc.identifier.scopusquality | N/A | |
| dc.identifier.uri | https://doi.org/10.1109/idap.2019.8875959 | |
| dc.identifier.uri | https://hdl.handle.net/11508/46093 | |
| dc.identifier.wos | WOS:000591781100087 | |
| dc.identifier.wosquality | N/A | |
| dc.indekslendigikaynak | Web of Science | |
| dc.indekslendigikaynak | Scopus | |
| dc.language.iso | en | |
| dc.publisher | Ieee | |
| dc.relation.ispartof | 2019 International Conference on Artificial Intelligence and Data Processing (Idap 2019) | |
| dc.relation.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | |
| dc.rights | info:eu-repo/semantics/closedAccess | |
| dc.snmz | KA_WoS_20260511 | |
| dc.subject | Fpga | |
| dc.subject | Histogram | |
| dc.subject | Image Enhancement | |
| dc.subject | Verilog | |
| dc.title | Simultaneously Realization of Image Enhancement Techniques On Real-Time Fpga | |
| dc.type | Conference Object |







